A power factor correction (PFC) converter requires alternating-current (AC) information and direct-current (DC) information of the input signal to the PFC converter for various applications, such as establishing a current in proportion to the waveform of the input signal, detecting the valley of the input signal, and determining total harmonic distortion (THD) to improve trip point by using the AC information, and determining the value of the input signal, achieving brown in/brown out protection, etc. by using the DC information. Traditionally, the DC information is obtained by detecting the peak or root-mean-square (RMS) value of the input signal.
FIG. 1 shows a traditional control integrated circuit (IC) 2 for a PFC converter. An AC voltage Vac supplied to the PFC converter is rectified by a bridge rectifier 4 and becomes an input signal Vin, which is divided by a divider circuit 6 to generate an input signal Vd for a pin MULT of the control IC 2. The control IC 2 may obtain the alternating-current information of the input signal Vin from the input signal Vd on the pin MULT. The PFC converter uses a signal peak detector 8 to detect the peak of the input signal Vd to obtain the DC information of the input signal Vin. In the signal peak detector 8, an ideal diode 10 consisting of a diode and an operational amplifier provides the input signal Vd to a capacitor C1, to generate a peak signal Vpeak. A conversion circuit 12 obtains the DC information of the input signal Vin according to the peak signal Vpeak. A resistor Rff connected in parallel to the capacitor C1 acts as a discharging path for allowing the capacitor C1 to discharge slowly. However, this method for detecting the DC information requires a large capacitor C1 to stabilize the peak signal Vpeak. Since such a large capacitor C1 cannot be integrated into the control IC 2, an additional pin VFF has to be used to connect the large capacitor C1 outside the control IC 2. Thus, the traditional PFC converter needs two pins MULT and VFF to obtain the alternating-current information and the DC information of the input signal Vin.
In addition, when the peak of the input signal Vin drops, the method using the capacitor C1 to obtain the peak signal Vpeak has relatively slow transient response. Particularly, referring to FIG. 2, between time points t1 and t2, the input signal Vin turns to a high peak from a low peak, and the peak signal Vpeak on the capacitor C1 soon raises to a second level VL2 from a first level VL1. However, when the input signal Vin turns from a high peak to a low peak, as happening between time points t3 and t4, since the capacitor C1 discharges slowly, the peak signal Vpeak will not drop to the first level VL from the second level VL2 until several cycles TP of the input signal Vin lapse. Thus, in the signal peak detector 8 of FIG. 1, when the input signal Vin has its peak turning from high to low, the transient response of the peak signal Vpeak is relatively slow.
In some applications, a PFC converter may give up the alternating-current information and only obtain the DC information in order to reduce the number of the pins required. FIG. 3, FIG. 4 and FIG. 5 show detectors for detecting the DC information without obtain the alternating-current information. FIG. 3 is a conventional RMS detector 14, which comprises a filter that consists of resistors R3 and R4 and a capacitor C1 and serves to obtain an RMS value Vrms of the input signal Vin for the control IC 2. The RMS value Vrms has the DC information of the input signal Vin, so the control IC 2 can accordingly obtain the DC information of the input signal Vin. FIG. 4 shows another signal peak detector 8, which comprises a capacitor C1, resistors R3, R4, Rff and a diode D1. The resistors R3 and R4 divide the input signal Vin to generate a input signal Vd. The input signal Vd charges the capacitor C1 via the diode D1 to generate a peak signal Vpeak for the control IC 2 such that the control IC 2 can accordingly obtain the DC information of the input signal Vin. The resistor Rff that is connected in parallel with the capacitor C1 acts as a discharging path for the capacitor C1 to discharge slowly. In the signal peak detector 8 of FIG. 4, the forward bias of the diode D1 causes an error between the peak signal Vpeak and the peak of the input signal Vd. This error can be eliminated by adding a diode D2 between an anode of the diode D1 and the resistor R4, as shown in FIG. 5. However, the detectors of FIG. 3, FIG. 4 and FIG. 5 also have the problem about slow transient response when the peak of the input signal Vin turns to low from high.
U.S. Pat. No. 6,731,230 teaches a signal peak detection method that detects an input signal to generate an output peak signal. During the input signal rises, if the output peak signal is smaller than the input signal, the output peak signal is risen in a relatively high speed. During the input signal falls, a reference voltage is used for detecting the input signal to remain the output peak signal at the peak voltage level of the input signal. When the input signal remains lower than the reference voltage over a predetermined number of clock cycles, the output peak signal is stopped from dropping with the input signal. However, this method also has the problem about slow transient response when the peak of the input signal turns to low from high.